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Conference Paper
Analysis of an Asynchronous RISC Processor Based on EISC Instruction Set Architecture
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- Issue Date
- 2012-07
- Citation
- International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC) 2012, pp.1-3
- Publisher
- IEEE
- Language
- English
- Type
- Conference Paper
- Abstract
- This paper analyzes the architecture of a self-timed processor which has been modeled by using a specialized CAD tool in designing asynchronous circuits. The processor complies with the reduced instruction set computer (RISC) styled architecture and the analysis was performed in terms of each stage by simulation using 0.13 um CMOS technology with gate-level netlists. Based on the lessons of the analysis, an alternative architectural features for the self-timed processor is also proposed in this paper.
- KSP Keywords
- Asynchronous circuits, CAD tool, CMOS Technology, Gate-level, Instruction set architecture, RISC processor, Reduced Instruction set computer(RISC), Self-timed, architectural features