BROWSE
Detail
Conference Paper
ASIP for Multi-Standard Video Decoding
Cited - time in 
Share 
Share
- Authors
- Jae-Jin Lee, KyungJin Byun, NakWoong Eum
- Issue Date
- 2012-08
- Citation
- International Conference on Advances in Circuits, Electronics and Micro-electronics (CENICS) 2012, pp.37-42
- Language
- English
- Type
- Conference Paper
- Abstract
- Multiple international video standards in the market have been developed successfully for many commercial products. Application-specific instruction processor is a new design methodology to develop optimized processor. This paper proposes a new application-specific instruction set processor based on 6-stage pipelined dual issue VLIW+SIMD architecture and compiler for multi-standard video decoding. The processor takes 130K in gate count at 125MHz in 130nm technology. Compared to the existing ARM processor, the proposed processor results in about 20% speed improvement as well as smaller hardware complexity.
- KSP Keywords
- ARM Processor, Application-specific instruction set processor, Commercial products, Hardware complexity, Multi-Standard, SIMD architecture, design methodology, video decoding