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Conference Paper
Compact Hardware Architecture for First One Detector using Priority-based Uniform Partition
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- Authors
- Mooseop Kim, Jong Wook Han
- Issue Date
- 2012-10
- Citation
- International Conference on Information and Communication Technology Convergence (ICTC) 2012, pp.179-180
- Publisher
- IEEE
- Language
- English
- Type
- Conference Paper
- Abstract
- This paper presents an optimized architecture for a first-one detector (FOD) using a uniform partition decoding scheme based on the statistical distribution of the input code words. The proposed architecture uses a conventional method to optimize the Boolean expression of the input code words. Experimental results show that the proposed approach covers only 58 gates in a 0.25 μm CMOS technology. Based on the result of our design, we can achieve a remarkable reduction of a hardware cost, which consumes less than 10% of the size of the implementation of previous works. © 2012 IEEE.
- KSP Keywords
- CMOS Technology, Conventional methods, Hardware Architecture, Optimized Architecture, Priority-Based, boolean expression, hardware cost, statistical distribution