상세정보
학술대회
Compact Hardware Architecture for First One Detector using Priority-based Uniform Partition
- 발행일
- 201210
- 출처
- International Conference on Information and Communication Technology Convergence (ICTC) 2012, pp.179-180
- 협약과제
- 12MG1400, 개인신변 안전보장을 위한 영상보안 기술개발, 한종욱
- 초록
- This paper presents an optimized architecture for a first-one detector (FOD) using a uniform partition decoding scheme based on the statistical distribution of the input code words. The proposed architecture uses a conventional method to optimize the Boolean expression of the input code words. Experimental results show that the proposed approach covers only 58 gates in a 0.25 μm CMOS technology. Based on the result of our design, we can achieve a remarkable reduction of a hardware cost, which consumes less than 10% of the size of the implementation of previous works. © 2012 IEEE.
- KSP 제안 키워드
- CMOS Technology, Conventional methods, Hardware Architecture, Optimized Architecture, Priority-Based, boolean expression, hardware cost, statistical distribution