상세정보
학술대회
Multi-Core Architecture for Video Decoding
- 발행일
- 201211
- 출처
- International SoC Design Conference (ISOCC) 2012, pp.2-5
- 협약과제
- 12VD1200, 다중코어 기반 고성능 SoC의 SW 에뮬레이션 및 Rapid Prototyping 기술개발, 변경진
- 초록
- Multiple international video standards in the market have been developed successfully for many commercial products. This paper proposes a new multimedia core and multi-core architecture for multi-standard video decoding. The proposed multimedia core is based on the 6-stage pipelined dual issue VLIW+SIMD architecture and efficient instructions for video decoding. SMIC 130nm process is used for implementation of the proposed architecture whose approximate gate count is about 130K and runs at 125MHz. The multi-core architecture consisting of eight multimedia cores is efficient for parallel decoding of various video compression formats including MPEG-2, MPEG-4, AVS and H.264/AVC. © 2012 IEEE.
- KSP 제안 키워드
- Commercial products, MPEG-2, Mpeg-4, Multi-Standard, Multi-core architecture, SIMD architecture, Video compression, parallel decoding, video decoding