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Conference Paper
Multi-Core Architecture for Video Decoding
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- Authors
- Jae-Jin Lee, KyungJin Byun, NakWoong Eum
- Issue Date
- 2012-11
- Citation
- International SoC Design Conference (ISOCC) 2012, pp.2-5
- Publisher
- IEEE
- Language
- English
- Type
- Conference Paper
- Abstract
- Multiple international video standards in the market have been developed successfully for many commercial products. This paper proposes a new multimedia core and multi-core architecture for multi-standard video decoding. The proposed multimedia core is based on the 6-stage pipelined dual issue VLIW+SIMD architecture and efficient instructions for video decoding. SMIC 130nm process is used for implementation of the proposed architecture whose approximate gate count is about 130K and runs at 125MHz. The multi-core architecture consisting of eight multimedia cores is efficient for parallel decoding of various video compression formats including MPEG-2, MPEG-4, AVS and H.264/AVC. © 2012 IEEE.
- KSP Keywords
- Commercial products, MPEG-2, Mpeg-4, Multi-Standard, Multicore architecture, SIMD architecture, Video compression, parallel decoding, video decoding