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Simulation Studies of Triple Gate Trench Power MOSFETs (TGRMOSs) by Using Modified Resurf Stepped Oxide (RSO) Process with Various Gate Configuration and its Bias Condition
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- Authors
- K.-I. Na, J.-I. Won, K. S. Park, J.-G. Koo, S.-G. Kim, J.-M. Park, S.-W. Yoo, Y.-S. Yang, J.-H. Lee
- Issue Date
- 2013-02
- Citation
- 한국 반도체 학술 대회 (KCS) 2013, pp.1-2
- Language
- English
- Type
- Conference Paper
- Abstract
- We propose the triple gate trench power MOSFETs (TGRMOS) using a modified resurf stepped oxide (RSO) process. This is that a single SiO2 thick-insulator layer of a conventional RSO power MOSFET is changed the multiple thick-insulator layers (SiO 2 /SiN x /TEOS) (called a 'nitride_RSO' process). The inserted SiNx layer can create the selective etching of the TEOS layer between the gate oxide and poly-Si layers. After additional oxidation and poly-Si filling processes, the three gate parts are automatically separated into three parts. Moreover, to confirm the variation in the electrical properties, such as BV DS and I D,MAX , of TGRMOS, simulation studies were performed on the function of the gate configurations and their bias conditions. BV DS and I D.MAX were controlled from 87 to 152 V, and from 0.14 to 0.24 mA at a gate voltage 15 V. This I D.MAX variation indicates the specific ON resistance modulation.
- KSP Keywords
- Gate oxide, Insulator layer, Polycrystalline silicon(poly-Si), Resistance modulation, SiN x, SiO 2, Simulation study, Triple-gate, electrical properties(I-V curve), gate voltage, selective etching