상세정보
학술지
Architectural Design Issues in a Clockless 32-Bit Processor Using an Asynchronous HDL
- 발행일
- 201306
- 출처
- ETRI Journal, v.35 no.3, pp.480-490
- ISSN
- 1225-6463
- 출판사
- 한국전자통신연구원 (ETRI)
- 협약과제
- 12ZS1100, 지식서비스기반 SW 핵심기술연구, 황승구
- 초록
- As technology evolves into the deep submicron level, synchronous circuit designs based on a single global clock have incurred problems in such areas as timing closure and power consumption. An asynchronous circuit design methodology is one of the strong candidates to solve such problems. To verify the feasibility and efficiency of a largescale asynchronous circuit, we design a fully clockless 32-bit processor. We model the processor using an asynchronous HDL and synthesize it using a tool specialized for asynchronous circuits with a top-down design approach. In this paper, two microarchitectures, basic and enhanced, are explored. The results from a pre-layout simulation utilizing 0.13-μm CMOS technology show that the performance and power consumption of the enhanced microarchitecture are respectively improved by 109% and 30% with respect to the basic architecture. Furthermore, the measured power efficiency is about 238 μW/MHz and is comparable to that of a synchronous counterpart. © 2013 ETRI.
- KSP 제안 키워드
- Architectural Design, Asynchronous circuits, CMOS Technology, Deep Submicron, Design issues, Global clock, Layout simulation, Power Consumption, Power Efficiency, Timing closure, Top-down design