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Conference Paper
High-speed LDPC Encoder Architecture for Digital Video Broadcasting Systems
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- Authors
- InKi Lee, MinHyuk Kim, DeockGil Oh, JiWon Jung
- Issue Date
- 2013-10
- Citation
- International Conference on Information and Communication Technology Convergence (ICTC) 2013, pp.606-607
- Publisher
- IEEE
- Language
- English
- Type
- Conference Paper
- Abstract
- In this paper, we propose a high-speed LDPC encoder architecture for the DVB-S2 standard. The proposed LDPC encoding architecture is based on parallel 360 bit-wise operations. The key issues for realizing a high speed are two kinds of index addresses and making efficient use of memory. We implemented a half-rate LDPC encoder on an FPGA, and confirmed that its maximum throughput is up to 10 Gbps with a 100 MHz clock. © 2013 IEEE.
- KSP Keywords
- 100 MHz, Broadcasting system, DVB-S2, Digital video broadcasting, High Speed, Key Issues, LDPC Encoder, LDPC encoding, bit-wise, maximum throughput