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학술대회 High-speed LDPC Encoder Architecture for Digital Video Broadcasting Systems
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저자
이인기, 김민혁, 오덕길, 정지원
발행일
201310
출처
International Conference on Information and Communication Technology Convergence (ICTC) 2013, pp.606-607
DOI
https://dx.doi.org/10.1109/ICTC.2013.6675433
협약과제
13PR2800, 채널 적응형 실감위성방송 전송기술 개발, 오덕길
초록
In this paper, we propose a high-speed LDPC encoder architecture for the DVB-S2 standard. The proposed LDPC encoding architecture is based on parallel 360 bit-wise operations. The key issues for realizing a high speed are two kinds of index addresses and making efficient use of memory. We implemented a half-rate LDPC encoder on an FPGA, and confirmed that its maximum throughput is up to 10 Gbps with a 100 MHz clock. © 2013 IEEE.
KSP 제안 키워드
100 MHz, Broadcasting system, DVB-S2, Digital video broadcasting, High Speed, Key Issues, LDPC Encoder, LDPC encoding, bit-wise, maximum throughput