BROWSE
Detail
Conference Paper
Si-interposer Design for GPU-Memory Integration concerning the Signal Integrity
Cited - time in 
Share 
Share
- Authors
- Jonghyun Cho, Joohee Kim, Hyun-Cheol Bae, Kwangseong Choi, Seungwook Paek, Lee-Sup Kim, Joungho Kim
- Issue Date
- 2013-01
- Citation
- DesignCon 2013, pp.1-20
- Language
- English
- Type
- Conference Paper
- Abstract
- Even 3-dimensional integrated circuit (3D-IC) has several advantages, it faces difficulties in the mass production due to the low-fabrication yields. As an alternative solution for 3D-IC, many companies pay attention to a 2.5D-IC with interposer. In this paper, we investigate various design issues of 2.5D Si-interposer for GPU-Memory system, which consists of GPU, memory, and Si-interposer. The Si-interposer is designed using 2-layer re-distribution layer (RDL) and TSV. In the design, the lossy silicon substrate and the limited number of RDL layers cause several design issues such as routability, signal loss, crosstalk, and impedance mismatching. Because our target data frequency is only 50 MHz, these issues cause only a small effect on signal integrity of our system. However, high bandwidth is generally required in Si-interposer and a Siinterposer design for maximum bandwidth is proposed by considering these design issues at the same time. Eye-diagram is used for the evaluation of Si-interposer signal integrity. The Si-interposer is designed considering these signal integrity issues and it is in progress of fabrication.
- KSP Keywords
- 2.5D-IC, 3-dimensional, 3D-IC, Design issues, Distribution layer, Eye diagram, Impedance mismatching, Memory System, Signal Integrity(SI), Signal loss, Silicon substrate