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Conference Paper
Study of Clock Synchronization for High Speed Satellite Communication Transmission
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- Authors
- Pansoo Kim, Deock-Gil Oh
- Issue Date
- 2013-10
- Citation
- World Congress on Engineering and Computer Science (WCECS) 2013, pp.1-5
- Language
- English
- Type
- Conference Paper
- Abstract
- This paper exemplifies one practical way to design high-speed symbol timing recovery using the parallel architecture to cope with time constraint of computational processing. Recently, as wideband satellite transponders that have 200 to 300MHz come out and active study is followed for efficient transmission in terms of power/bandwidth based on single carrier transmission. When taking into account a single carrier transmission, receiver for instance should be able to work at maximum 250MHz symbol rate on 300MHz transponder bandwidth. However, straightforward parallel processing entails increased amount of computational logic and makes it difficult for massive ASIC chipset production. As a result, this paper specifies efficient parallel processing of blocks susceptible to processing latency and manifests its effectiveness by means of performance assessment and FPGA implementation.
- KSP Keywords
- Clock Synchronization, FPGA Implementation, High Speed, Parallel Architecture, Parallel Processing, Performance Assessment, Single-carrier(SC), Symbol timing recovery, computational logic, efficient transmission, satellite communication