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Journal Article A Hardware-Efficient Pattern Matching Architecture Using Process Element Tree for Deep Packet Inspection
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Authors
Seongyong AHN, Hyejeong HONG, HyunJin KIM, Jin-Ho AHN, Dongmyong BAEK, Sungho KANG
Issue Date
2010-09
Citation
IEICE Transactions on Communications, v.E93.B, no.9, pp.2440-2442
ISSN
0916-8516
Publisher
일본, 전자정보통신학회 (IEICE)
Language
English
Type
Journal Article
DOI
https://dx.doi.org/10.1587/transcom.E93.B.2440
Abstract
This paper proposes a new pattern matching architecture with multi-character processing for deep packet inspection. The proposed pattern matching architecture detects the start point of pattern matching from multi-character input using input text alignment. By eliminating duplicate hardware components using process element tree, hardware cost is greatly reduced in the proposed pattern matching architecture. Copyright © 2010 The Institute of Electronics, Information and Communication Engineers.
KSP Keywords
Character input, Element tree, Hardware efficient, Information and communication, Processing engine(PE), deep packet inspection(DPI), hardware cost, pattern matching, text alignment