상세정보
학술지
A Hardware-Efficient Pattern Matching Architecture Using Process Element Tree for Deep Packet Inspection
- 저자
- 안성용, 홍혜정, 김현진, 안진호, 백동명, 강성호
- 발행일
- 201009
- 출처
- IEICE Transactions on Communications, v.E93.B no.9, pp.2440-2442
- ISSN
- 0916-8516
- 출판사
- 일본, 전자정보통신학회 (IEICE)
- 협약과제
- 10MI2800, Scalable 마이크로 플로우 처리기술개발, 이범철
- 초록
- This paper proposes a new pattern matching architecture with multi-character processing for deep packet inspection. The proposed pattern matching architecture detects the start point of pattern matching from multi-character input using input text alignment. By eliminating duplicate hardware components using process element tree, hardware cost is greatly reduced in the proposed pattern matching architecture. Copyright © 2010 The Institute of Electronics, Information and Communication Engineers.
- KSP 제안 키워드
- Character input, Element tree, Hardware efficient, Information and communication, Processing engine(PE), deep packet inspection(DPI), hardware cost, pattern matching, text alignment