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Journal Article
Design and Implementation of a Latency Efficient Encoder for LTE Systems
- Authors
- Soo Yun Hwang, Dae Ho Kim, Kyoung Son Jhang
- Issue Date
- 2010-08
- Citation
- ETRI Journal, v.32, no.4, pp.493-502
- ISSN
- 1225-6463
- Publisher
- 한국전자통신연구원 (ETRI)
- Language
- English
- Type
- Journal Article
- Abstract
- The operation time of an encoder is one of the critical implementation issues for satisfying the timing requirements of Long Term Evolution (LTE) systems because the encoder is based on binary operations. In this paper, we propose a design and implementation of a latency efficient encoder for LTE systems. By virtue of 8-bit parallel processing of the cyclic redundancy checking attachment, code block (CB) segmentation, and a parallel processor, we are able to construct engines for turbo codings and rate matchings of each CB in a parallel fashion. Experimental results illustrate that although the total area and clock period of the proposed scheme are 19% and 6% larger than those of a conventional method based on a serial scheme, respectively, our parallel structure decreases the latency by about 32% to 65% compared with a serial structure. In particular, our approach is more latency efficient when the encoder processes a number of CBs. In addition, we apply the proposed scheme to a real system based on LTE, so that the timing requirement for ACK/NACK transmission is met by employing the encoder based on the parallel structure. © ETRI 2010.
- KSP Keywords
- Clock Period, Conventional methods, LTE system, Long Term Evolution(LTE), Parallel Processing, Parallel processor, Parallel structure, design and implementation, timing requirements