ETRI-Knowledge Sharing Plaform



논문 검색
구분 SCI
연도 ~ 키워드


학술지 Design and Implementation of a Latency Efficient Encoder for LTE Systems
Cited 7 time in scopus Download 4 time Share share facebook twitter linkedin kakaostory
황수연, 김대호, 장경선
ETRI Journal, v.32 no.4, pp.493-502
한국전자통신연구원 (ETRI)
09MR1700, 4세대 이동통신을 위한 적응 무선접속 및 전송 기술개발, 김영진
The operation time of an encoder is one of the critical implementation issues for satisfying the timing requirements of Long Term Evolution (LTE) systems because the encoder is based on binary operations. In this paper, we propose a design and implementation of a latency efficient encoder for LTE systems. By virtue of 8-bit parallel processing of the cyclic redundancy checking attachment, code block (CB) segmentation, and a parallel processor, we are able to construct engines for turbo codings and rate matchings of each CB in a parallel fashion. Experimental results illustrate that although the total area and clock period of the proposed scheme are 19% and 6% larger than those of a conventional method based on a serial scheme, respectively, our parallel structure decreases the latency by about 32% to 65% compared with a serial structure. In particular, our approach is more latency efficient when the encoder processes a number of CBs. In addition, we apply the proposed scheme to a real system based on LTE, so that the timing requirement for ACK/NACK transmission is met by employing the encoder based on the parallel structure. © ETRI 2010.
KSP 제안 키워드
Clock Period, Conventional methods, LTE systems, Long term Evolution(LTE), Parallel Processing, Parallel processor, Parallel structure, design and implementation, timing requirements