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A 230ns settling time type-I PLL with 0.96mW TDC power and simple T<inf>V</inf> calculation algorithm
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- Authors
- Ja-Yol Lee, Mi-Jeong Park, Hyun-Kyu Yu, Cheon-Soo Kim
- Issue Date
- 2014-08
- Citation
- International Midwest Symposium on Circuits and Systems (MWSCAS) 2014, pp.370-373
- Language
- English
- Type
- Conference Paper
- Abstract
- This paper describes a fast-settling all-digital PLL with a low-power TDC based on retimed reference clock and a lock detector focused on monitoring a toggling phase error. With the intention of reducing power dissipation, the proposed TDC employs the low-rate reference (CKfref) and retimed reference (CKfros) clocks to measure the fine fractional phase error between the low-rate reference (CKfref) and high-rate oscillator (CKfosc) clocks. In addition, the use of the retimed reference clock to the TDC results in a new simple DCO clock period (TV) calculation algorithm which employs the maximum and minimum values for the fractional error correction (琯). A lock detector, which is required to accomplish the switchover of the DCO frequency tuning mode, allows a fast settling to be actuated independent of loop bandwidth and frequency step. By dissipating 8mW at 1.2-V supply voltage, the proposed digital PLL achieves 230ns settling time, 1.7psrms period jitter.
- KSP Keywords
- All-digital PLL, Calculation algorithm, Clock Period, Error Correction, Fast Settling, Frequency tuning, High rate, Lock Detector, Low-Power, Low-rate, Reducing power