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A FPGA based Real-Time Post-Processing Architecture for Active Stereo Vision
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- Authors
- Seung-min Choi, Jiho Chang, Dae Hwan Hwang
- Issue Date
- 2014-06
- Citation
- International Symposium on Consumer Electronics (ISCE) 2014, pp.1-2
- Publisher
- IEEE
- Language
- English
- Type
- Conference Paper
- Abstract
- This paper presents a post-processing architecture for high quality depth map in active stereo vision. The proposed architecture consists of five sub-blocks in cascade manner, which are consistency check, hole filling, variance check, weighted median filter, and joint bilateral filter. The novel design which is implemented on a single FPGA achieves 60 frames per second for 1280×720 stereo images with 256 disparity range. © 2014 IEEE.
- KSP Keywords
- Active stereo vision, Depth Map, Frames per second(FPS), Joint Bilateral Filter, Post-Processing, Processing architecture, Real-time, Sub-Blocks(SB), Weighted median filter, consistency check, hole filling