상세정보
학술대회
Automatic Construction of Timing Diagrams from UML/MARTE Models for Real-Time Embedded Software
- 저자
- 차우, 지은경, 최진호, 배두환
- 발행일
- 201403
- 출처
- Symposium on Applied Computing (SAC) 2014, pp.1140-1145
- 협약과제
- 13PS1500, 다수의 이종 클라우드 자원을 통합 관리하는 서비스 브로커 및 개방형 빅데이터 분석?협업 플랫폼 개발, 정성인
- 초록
- Analysis of timing constraints is an essential part in developing real-time embedded software. Performing the timing analysis during the early development phases prevents timing violations and enhances software quality. In the development of real-time embedded software, UML timing diagrams can play a significant role since they can provide not only intuitive specifications for timing constraints, but also valuable information for verifying system requirements. However, as software complexity increases, modeling timing diagrams is becoming difficult and costly. We propose an automated construction approach of timing diagrams from UML sequence diagrams and state machine diagrams with MARTE annotations. The proposed approach enables developers of RTES to save time required for modeling timing diagrams and prevents making mistakes in construction of timing diagrams. Copyright 2014 ACM.
- KSP 제안 키워드
- Automatic construction, Early development phases, Real-time embedded software, Software analysis, State machine, System Requirements, Timing Analysis, Timing Diagrams, UML sequence diagrams, software complexity, software quality