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학술대회 Compact 10 ~ 13 GHz GaN Low Noise Amplifier MMIC using Simple Matching and Bias Circuits
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저자
장우진, 박영락, 문재경, 고상춘, 전계익
발행일
201410
출처
European Microwave Integrated Circuits Conference (EuMIC) 2014, pp.516-519
DOI
https://dx.doi.org/10.1109/EuMIC.2014.6997907
협약과제
14MB1200, 스마트 데이터센터용 차세대 광-전 모듈 기술, 남은수
초록
A compact 10 ~ 13 GHz low-noise amplifier (LNA) monolithic microwave integrated circuit (MMIC) using simple matching and bias circuits is designed and fabricated using AlGaN/GaN 0.25 μm high electron mobility transistor (HEMT) technology on silicon carbide (SiC) substrate. In order to reduce the chip size and simplify the structure of the LNA, the matching and bias circuits were combined functionally and structurally together and the meandered microstriplines were used. And the combined circuits also contributed to decrease the noise figure of the LNA. Therefore, the measured noise figures of the LNA are almost equal to the minimum noise figure of 2 × 100 μm device which was used for the first stage of the LNA. And also the chip size of the fabricated LNA is 1.7 × 0.8 mm2 including two ground-signal-ground (GSG) pads and the DC pads on the chip. The LNA shows a noise figure of 1.7 ~ 2.1 dB with a gain of 19 ~ 26 dB across the 10 ~ 13 GHz frequency range. In continuous wave (CW) conditions, it presents a saturated output power of 29 ~ 34 dBm for 10 ~ 13 GHz and also the output third-order intercept point (OIP3) of 42 dBm at 11.4 GHz.
키워드
Chip size reduction, GaN, LNA, matching circuit
KSP 제안 키워드
First stage, Frequency Range, High electron mobility transistor(HEMT), Intercept point(IIP3), Microwave monolithic integrated circuits(MMIC), Minimum noise figure, Noise Figure(NF), Saturated output power, bias circuit, chip size reduction, continuous wave(CW)