상세정보
학술대회
Design and Measurement of 500-MS/s ΣΔ Modulator with Half-delayed Return-to-zero Feedback DAC
- 발행일
- 201410
- 출처
- European Microwave Integrated Circuits Conference (EuMIC) 2014, pp.273-276
- 협약과제
- 14MI9100, (통합)초연결 스마트 모바일 서비스를 위한 5G 이동통신 핵심기술개발, 정현규
- 초록
- A second-order continuous-time (CT) low-pass 誇?? modulator using a single feedback digital-to-analog converter (DAC) is presented. To reduce the feedback DACs by one, we introduce half-delayed return-to-zero (HRZ) feedback signaling and feed-forward topology. The HRZ feedback scheme reduces power consumption and die area by removing a summing amplifier and DAC for the excess-loop delay compensation and the feed-forward topology saves additional power and area by replacing the feedback DAC with feed-forward path. The concept is implemented in a 500 MS/s CT 誇?? modulator for 12-MHz signal bandwidth in a 130 nm CMOS process which occupies 0.19 mm2. The Measurements show that the modulator achieves spurious free dynamic range of 61.2 dB, signal-to-noise and distortion ratio of 52.5 dB, and dynamic range of 55 dB. The modulator consumes 9.96 mW at a 1.2 V supply.
- KSP 제안 키워드
- 130 nm, CMOS Process, Continuous-Time, Digital to Analog Converter, Distortion ratio, Feed-Forward Path, Loop delay, Power Consumption, Signal-to-Noise, delay compensation, digital-to-analog(DAC)