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Conference Paper
Multi-Core based HEVC Hardware Decoding System
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- Authors
- Hyunmi Kim, Seunghyun Cho, Kyungjin Byun, Nak-Woong Eum
- Issue Date
- 2014-07
- Citation
- International Conference on Multimedia and Expo Workshops (ICMEW) 2014, pp.1-2
- Language
- English
- Type
- Conference Paper
- Abstract
- In this demo, a scalable HEVC hardware decoder is demonstrated for various applications including UHD. The architecture includes a control logic for multi-core management and flexible in-loop filters that can process boundaries of picture partitions without a separate in-loop filter unit from the pipeline. Two-level parallel processing approach makes the decoder operate in real-time for high-performance applications. The demonstration on FPGA prototype board shows the efficiency of the proposed scalable architecture achieved by multi-core design. The system is estimated to be able to decode UHD video coded by HEVC in real-time.
- KSP Keywords
- Control logic, FPGA prototype, In-Loop Filter, Parallel Processing, Real-time, Scalable HEVC, Two-level, UHD video, high-performance applications, loop-filter(LF), multi-Core