상세정보
학술대회
Multi-Core based HEVC Hardware Decoding System
- 발행일
- 201407
- 출처
- International Conference on Multimedia and Expo Workshops (ICMEW) 2014, pp.1-2
- 협약과제
- 14PS1200, 초고해상도 비디오 코덱 SoC, 엄낙웅
- 초록
- In this demo, a scalable HEVC hardware decoder is demonstrated for various applications including UHD. The architecture includes a control logic for multi-core management and flexible in-loop filters that can process boundaries of picture partitions without a separate in-loop filter unit from the pipeline. Two-level parallel processing approach makes the decoder operate in real-time for high-performance applications. The demonstration on FPGA prototype board shows the efficiency of the proposed scalable architecture achieved by multi-core design. The system is estimated to be able to decode UHD video coded by HEVC in real-time.
- KSP 제안 키워드
- Control logic, FPGA prototype, In-Loop Filter, Parallel Processing, Real-Time, Scalable HEVC, Two-level, UHD video, high-performance applications, loop-filter(LF), multi-Core