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학술대회 Power Noise Isolation in a Silicon Interposer with Through Silicon Vias
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저자
김명회, 신동환, 엄만석, 염인복
발행일
201412
출처
Electronics Packaging Technology Conference (EPTC) 2014, pp.805-808
DOI
https://dx.doi.org/10.1109/EPTC.2014.7028315
협약과제
14MR3100, 차기위성 Flexible 통신방송 탑재체 핵심기술 개발, 안재영
초록
In this paper, we present a new structure of a power distribution network (PDN) in silicon interposers with through silicon vias (TSVs) to suppress the high-frequency power/ground noise including simultaneous switching noise. The proposed PDN structure employs the resonant structure consisting of metal patterns and TSVs. To examine the effect of design parameters of the resonant structure on noise suppression characteristics, we present Bloch analysis based on a phase of Bloch impedance and Floquet's theorem. Simulation results show a good correlation between Bloch analysis and a full-wave simulation. Power noise isolation of the proposed PDN structure is verified using full-wave simulations.
KSP 제안 키워드
Distribution network(DN), Full-wave simulation, High Frequency(HF), Metal pattern, Power distribution network, Power noise, Resonant structure, Simultaneous switching noise, Through silicon vias(TSV), design parameters, noise isolation