BROWSE
Detail
Conference Paper
The Memory Core in 3D Die-Stacked DRAM
Cited - time in 
Share 
Share
- Authors
- Yongjoo Kim, Taeho Kim, Chaedeok Lim
- Issue Date
- 2014-05
- Citation
- International Symposium on Embedded Technology (ISET) 2014, pp.1-2
- Language
- English
- Type
- Conference Paper
- Abstract
- With the growth of technology and the improvement of architecture, contemporary von Neumann computer system can execute most of applications efficiently. Nevertheless, some memory intensive applications that access memory irregularly and have large dataset expose the limitations of the von Neumann computer system on the low cache efficiency. Therefore, these applications suffer from significant memory stall time in the conventional computer system. In this paper, we proposed a computer system model that consists of conventional system and 3D die-stacked memory containing co-processor within its logic layer to address the memory-wall problem.
- KSP Keywords
- Computer systems, Conventional System, Large datasets, Logic layer, Memory intensive applications, Stacked Memory, Von Neumann, co-processor, die-stacked dram, system model