상세정보
학술대회
An Efficient Motion Estimation Hardware Architecture using Modified Reference Data Access(MRDAS) Skip Algorithm for High Efficiency Video Coding(HEVC) Encoder
- 발행일
- 201609
- 출처
- International Conference on Consumer Electronics (ICCE) 2016 : Berlin, pp.88-92
- 협약과제
- 15IS1100, SOT기반 모션제어 컨트롤 플랫폼용 interactive 스마트웨어 기술 개발, 강성원
- 초록
- In this paper, we propose an efficient motion estimation hardware architecture for High Efficiency Video Coding (HEVC) using a Modified Reference Data Access Skip (MRDAS) for reducing the minimum memory bandwidth. The memory bandwidth is responsible for the throughput limitations in motion estimation, especially when dealing with high quality video of a large frame size and search range. This architecture is designed for reducing the memory bandwidth using a memory access sequence and MRDAS. We save about 80% of the memory access cycles for the reference data compared to a conventional method with about 0.2 dB video quality degradation. The architecture is designed in Verilog HDL with a 65 nm cell library. The simulation results show that the architecture can achieve real-time processing of a 3,840 × 2,160 video image size at 30 fps at 350 MHz.
- KSP 제안 키워드
- 65 nm, Cell library, Conventional methods, Data Access, Frame size, Hardware Architecture, Memory Access, Memory bandwidth, Motion estimation(ME), Quality degradation, Real-Time processing