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학술대회 Reduced Complexity Single Core based HEVC Video Codec Processor for mobile 4K-UHD Applications
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저자
이석호, 김현미, 엄낙웅
발행일
201609
출처
International Conference on Consumer Electronics (ICCE) 2016 : Berlin, pp.97-98
DOI
https://dx.doi.org/10.1109/ICCE-Berlin.2016.7684727
협약과제
16HB1200, 스마트 디바이스용 지능형 반도체 공통 플랫폼 기술 개발, 이재진
초록
A future video codec processor will have to adopt the newly standardized High Efficiency Video Coding (HEVC/H.265) in a short time due to the limit of H.264's coding efficiency for large sized UHD images. This paper combines our designed decoder and encoder for HEVC and proposes a low complexity HEVC video codec processor. We developed this codec processor with Samsung 28nm CMOS process in this year and the size of this low complexity codec keeps within the bounds of that of a conventional H.264/AVC chip. This single core based processor has an optimal mode decision with a simplified Rate Distortion Optimization (RDO) and a low power Skip mode. The encoder's BD-rate loss is 35% compared with HM-13.0 and the power consumption is below 250mW when entering the Skip mode. The chip and its internal SRAM size are 7.3 × 7.5mm2 and 300kB each and the maximum frequency is 600MHz when 4K-UHD encoding mode at 30 fps.
KSP 제안 키워드
CMOS Process, Coding efficiency, Low-Power, Maximum Frequency, Mode decision, Power Consumption, Rate-Distortion Optimization(RDO), Reduced complexity, Short time, Skip mode, UHD images