상세정보
학술대회
A Mixed-radix Pipeline FFT Processor with Trivial Multiplication for LTE Uplink
- 발행일
- 201609
- 출처
- International Symposium on Consumer Electronics (ISCE) 2016, pp.57-58
- 협약과제
- 16MH2500, 100G용 Coherent OFDM DSP 개발, 강헌식
- 초록
- This paper presents a pipelined fast Fourier transform (FFT) processor consisting of radix-2, 3 and 5 for prime-sized discrete Fourier transform (DFT). The FFT processor does not require memory storing the twiddle factors or complex multiplications. It is adaptable for 34 kinds of the FFT length with a trivial multiplications and multiplexing of data in the LTE uplink. The proposed architecture reduces hardware complexity 32 %, and shows 737 Mbps throughput.
- KSP 제안 키워드
- FFT processor, Fast fourier transform (fft), Hardware complexity, LTE uplink, Mixed-radix, Multiplexing of Data, Radix-2, Twiddle Factor, discrete Fourier Transform