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A mixed-radix pipeline FFT processor with trivial multiplications for LTE uplink
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- Authors
- Jinkyu Kim, Juyeob Kim, Joohyun Lee, Kyoungrok Cho
- Issue Date
- 2016-09
- Citation
- International Symposium on Consumer Electronics (ISCE) 2016, pp.57-58
- Publisher
- IEEE
- Language
- English
- Type
- Conference Paper
- Abstract
- This paper presents a pipelined fast Fourier transform (FFT) processor consisting of radix-2, 3 and 5 for prime-sized discrete Fourier transform (DFT). The FFT processor does not require memory storing the twiddle factors or complex multiplications. It is adaptable for 34 kinds of the FFT length with a trivial multiplications and multiplexing of data in the LTE uplink. The proposed architecture reduces hardware complexity 32 %, and shows 737 Mbps throughput.
- KSP Keywords
- FFT processor, Fast Fourier Transform(FFI), Hardware Complexity, LTE uplink, Mixed-radix, Multiplexing of Data, Radix-2, Twiddle Factor, discrete Fourier Transform, fast fourier transform (fft)