상세정보
학술대회
An H.265/HEVC 4K UHD Slim Codec Design with Shared Prediction Unit Architecture
- 발행일
- 201610
- 출처
- International SoC Design Conference (ISOCC) 2016, pp.336-337
- 협약과제
- 16HB1200, 스마트 디바이스용 지능형 반도체 공통 플랫폼 기술 개발, 이재진
- 초록
- H.265/High Efficiency Video Coding (HEVC) is the latest next generation video compression standard posterior to H.264/AVC. However, despite its superior coding efficiency to the previous video coding standards, the complexity to implement it is an obstacle to overcome. Especially, combining the separate encoder and decoder has a disadvantage on the aspect of the size and power consumption. To solve these problems, we design an encoder based H.265/HEVC 4K slim codec. The decoder within this codec shares the prediction unit of encoder except an entropy decoder. The proposed shared prediction unit architecture saves the total size by 40 % compared to an independent codec with encoder and encoder separately. The size of logic is 2.8 M gates with 120 kB internal SRAM and the power consumption of this slim codec is within a level of encoder. The function of slim codec is verified on our designed the Xilinx Virtex-7 platform and the 4K UHD codec chip operating at 600 MHz is going to implement on a 28 nm CMOS process in this year.
- KSP 제안 키워드
- 28 nm CMOS, CMOS Process, Coding efficiency, Encoder and Decoder, Power Consumption, Video compression, Xilinx virtex, high efficiency video coding, prediction unit, video coding standard