상세정보
학술지
Cost Effective Silica-Based 100 G DP-QPSK Coherent Receiver
- 발행일
- 201610
- 출처
- ETRI Journal, v.38 no.5, pp.981-987
- ISSN
- 1225-6463
- 출판사
- 한국전자통신연구원 (ETRI)
- 협약과제
- 15MB1200, 소프트웨어 정의 네트워크(SDN) 기반 Flexible 광노드 핵심기술 개발, 권용환
- 초록
- We present a cost-effective dual polarization quadrature phase-shift coherent receiver module using a silica planar lightwave circuit (PLC) hybrid assembly. Two polarization beam splitters and two 90? optical hybrids are monolithically integrated in one silica PLC chip with an index contrast of 2%-??. Two four-channel spot-size converter integrated waveguide-photodetector (PD) arrays are bonded on PD carriers for transverse-electric/ transverse-magnetic polarization, and butt-coupled to a polished facet of the PLC using a simple chip-To-chip bonding method. Instead of a ceramic sub-mount, a lowcost printed circuit board is applied in the module. A stepped CuW block is used to dissipate the heat generated from trans-impedance amplifiers and to vertically align RF transmission lines. The fabricated coherent receiver shows a 3-dB bandwidth of 26 GHz and a common mode rejection ratio of 16 dB at 22 GHz for a local oscillator optical input. A bit error rate of 8.3 × 10-11 is achieved at a 112-Gbps back-To-back transmission with off-line digital signal processing.
- KSP 제안 키워드
- 100 G, 3-dB bandwidth, 6 GHz, Bit Error Rate(And BER), Coherent receiver, Common Mode Rejection Ratio, DP-QPSK, Digital Signal Processing, Dual-polarization, Four-Channel, Hybrid assembly