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Real-time 25-Gb/s EPON OLT MAC/PHY with a Single FPGA for 100-Gb/s Access Networks
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- Authors
- KwangOk Kim, KyeongHwan Doo, HwanSeok Chung
- Issue Date
- 2016-11
- Citation
- Asia Communications and Photonics Conferene (ACP) 2016, pp.1-3
- Publisher
- IEEE
- Language
- English
- Type
- Conference Paper
- Abstract
- We implement an efficient, asymmetric 25-Gb/s Ethernet PON (EPON) OLT MAC/PHY that can support a rate of 25.78125-Gb/s in the downstream direction and 10.3125- Gb/s in the upstream direction, based on a single FPGA. We design based on the IEEE 802.3av 10G-EPON standard, and it includes a 25-Gb/s PCS/PMA and burst-mode 10-Gb/s PCS/PMA. In this paper, we demonstrate that the proposed the 25-Gb/s EPON OLT MAC/PHY can guarantee error-free packet service during a 72-h run time, and provide a packet throughput of 24-Gb/s and 9.6-Gb/s in downstream and upstream paths through a back-to-back link configuration.
- KSP Keywords
- 10G-EPON, Asymmetric 2, Back to Back(BTB), Burst-mode, Downstream direction, IEEE 802.3av, Packet service, Real-time, Run-Time, access network, mode 1