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학술대회 Real-time 25-Gb/s EPON OLT MAC/PHY with a Single FPGA for 100-Gb/s Access Networks
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저자
김광옥, 두경환, 정환석
발행일
201611
출처
Asia Communications and Photonics Conferene (ACP) 2016, pp.1-3
DOI
https://dx.doi.org/10.1364/ACPC.2016.AF2A.91
협약과제
16MH1100, SDN 기반 유무선 액세스 통합 광네트워킹 기술, 정환석
초록
We implement an efficient, asymmetric 25-Gb/s Ethernet PON (EPON) OLT MAC/PHY that can support a rate of 25.78125-Gb/s in the downstream direction and 10.3125- Gb/s in the upstream direction, based on a single FPGA. We design based on the IEEE 802.3av 10G-EPON standard, and it includes a 25-Gb/s PCS/PMA and burst-mode 10-Gb/s PCS/PMA. In this paper, we demonstrate that the proposed the 25-Gb/s EPON OLT MAC/PHY can guarantee error-free packet service during a 72-h run time, and provide a packet throughput of 24-Gb/s and 9.6-Gb/s in downstream and upstream paths through a back-to-back link configuration.
KSP 제안 키워드
10G-EPON, Asymmetric 2, Downstream direction, IEEE 802.3av, Packet service, Real-Time, Run time, access network, back-to-back, burst mode, mode 1