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학술지 Tutorial: Design and Optimization of Power Delivery Networks
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저자
이우주
발행일
201610
출처
IEIE Transactions on Smart Processing and Computing, v.5 no.5, pp.1-9
ISSN
2287-5255
출판사
대한전자공학회 (IEIE)
DOI
https://dx.doi.org/10.5573/IEIESPC.2016.5.5.1
협약과제
16ZS1200, 초저에너지 프로세서를 위한 NZV 마이크로그레인 아키텍처 기술, 이재진
초록
The era of the Internet of Things (IoT) is upon us. In this era, minimizing power consumption becomes a primary concern for system-on-chip designers. While traditional power minimization and dynamic power management (DPM) techniques have been heavily explored to improve the power efficiency of devices inside very large-scale integration (VLSI) platforms, there is one critical factor that is often overlooked, which is the power conversion efficiency of a power delivery network (PDN). This paper is a tutorial that focuses on the power conversion efficiency of the PDN, and introduces novel methods to improve it. Circuit-, architecture-, and system-level approaches are presented to optimize PDN designs, while case studies for three different VSLI platforms validate the efficacy of the introduced approaches.
KSP 제안 키워드
Case studies, Conversion efficiency(C.E.), Critical factors, Design and optimization, Dynamic power management, Internet of thing(IoT), Power Consumption, Power Efficiency, Power Minimization, System-On-Chip(SoC), Very Large Scale Integration(VLSI)