상세정보
학술대회
HW/SW co-design of Face Detection & Recognition on Virtual Platform
- 발행일
- 201610
- 출처
- International Conference on Consumer Electronics (ICCE) 2016 : Asia, pp.307-308
- 협약과제
- 16MS3200, 이종 멀티코어 클러스터 기반 스마트 디바이스용 하이퍼커넥션 서비스 지원 SW-SoC 융합 플랫폼 핵심 기술, 임채덕
- 초록
- In this paper, we present a FPGA implementation of face detection hardware (HW) and also address face recognition software (SW) on virtual platform. We apply very deeply-cascaded classifier which is composed of heterogeneous feature-classifiers to capture various characteristics of images. We use 2 step classifiers, the first searches for the coarse features and the second for the fine features. Both of the features are composed of HAAR like feature classifiers and Gabor classifiers while the 1st coarse classifier uses 700 classifiers and the 2nd uses 1350 classifiers. For the very-deeply cascaded face detector, we developed dedicated HW engine to process a feature per a cycle. The face detection is implemented in a Xilinx Virtex-7 device. For face recognition SW co-design, we also developed a virtual platform (VP). We co-verified face detection engine and face recognition SW running on a conventional operating system (OS) using the VP. Face detector operates over 30 frame/s at 50 MHz frequency for real-Time applications up-To 640x480 size image.
- KSP 제안 키워드
- Cascaded classifier, FPGA Implementation, Face detection, HW-SW Codesign, Haar-Like features, Heterogeneous Feature, Real-time application, Virtual platform, Xilinx virtex, face recognition, operating system