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A Simple and Fast Giga Link between a Host and a FPGA
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- Authors
- Hoo-Sung Lee, Ik-Jae Chun, Moon-Sik Lee, Ji-Hoon Kim
- Issue Date
- 2016-02
- Citation
- 한국 반도체 학술 대회 (KCS) 2016, pp.1-1
- Language
- English
- Type
- Conference Paper
- Abstract
- We present a SG Link (Simple Giga Link) supporting simple and fast data transfer between a host and a FPGA/ASIC over a USB 3.0 interface. It makes high-bandwidth multiful streaming and memory mapped accesses possible. Versatile memory-mapped access can configure registers and initialize internal memory connected to the local wishbone interconnection in user logic [1]. A user application can communicate with a local FPGA through simple APIs including functions to read and write addressable data blocks with hiding the complexity of the USB 3.0 protocols. As shown in Figure 1, the SG Link includes a host software library for read and write, a firmware for the Cypress FX3 USB 3.0 device controller, and a Wishbone bus master logic with GPIF(General Purpose InterFace) interface in the FPGA [2]. For read operation, the read request contains the address and transfer length. For write operation, the write request additionally contains the write. The response for the read request contains thestatus and the read data, but the the write request returns only the status. It was applied to prototype system for a Gigabit Proximity Wireless Communication, we confirm data transfer operations between a host PC and a prototype board over 2 Gbps (250Mbytes/sec) data throughtput at application layer.
- KSP Keywords
- Data Blocks, Fast data transfer, Prototype system, Software library, USB 3.0, Wishbone bus, application layer, high-bandwidth, transfer length, wireless communication