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낮은 트리거 전압 기술을 이용한 MOSFET 기반 ESD 보호회로의 특성 비교에 관한 연구
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- Issue Date
- 2016-11
- Citation
- 대한전자공학회 학술 대회 (추계) 2016, pp.200-203
- Publisher
- 대한전자공학회
- Language
- Korean
- Type
- Conference Paper
- Abstract
- Electrostatic discharge (ESD) damage has become the main reliability issue for deep-submicron CMOS integrated circuit. This paper presents comparisons of ESD protection circuits using low trigger techniques in a 0.13 um CMOS process, Transmission line pulse (TLP) and human body model (HBM) results support the findings presented in this paper.
- KSP Keywords
- CMOS Process, CMOS integrated circuit, ESD protection, Electro Static Discharge(ESD), Protection circuit, Reliability issue, human body model, integrated circuit(IC), transmission line pulse(TLP)