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Fractional spur reduction technique using 45° phase dithering in phase interpolator based all‐digital phase‐locked loop
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- Issue Date
- 2016-11
- Citation
- Electronics Letters, v.52, no.23, pp.1920-1922
- ISSN
- 0013-5194
- Publisher
- IET
- Language
- English
- Type
- Journal Article
- Abstract
- A spur reduction technique in fractional-N phase-locked loops based on a current-mode phase interpolator (CMPI) is presented by dithering input signals of the CMPI. CMPI shows deterministic phase error having symmetrical profile around 45째 offset in each quadrant, and this non-linear property leads to fractional spurs. The proposed 45째 phase rotator with digital compensation reduces the fractional spur by 18.57 dB at most, and average improvement of fractional tones is 7.89 dB in 2 MHz frequency step measurement.
- KSP Keywords
- Current-mode(CM), Digital compensation, Fractional spur, Non-linear property, Reduction technique, fractional-n, phase error, phase interpolator, phase rotator, phase-locked loop(PLL), spur reduction