상세정보
학술지
Fractional Spur Reduction Technique using 45° Phase Dithering in Phase Interpolator based All-digital Phase-locked Loop
- 발행일
- 201611
- 출처
- Electronics Letters, v.52 no.23, pp.1920-1922
- ISSN
- 0013-5194
- 출판사
- IET
- 협약과제
- 16PB1600, Web 기반 어플리케이션 최적화 가상머신 가속엔진 개발, 구본태
- 초록
- A spur reduction technique in fractional-N phase-locked loops based on a current-mode phase interpolator (CMPI) is presented by dithering input signals of the CMPI. CMPI shows deterministic phase error having symmetrical profile around 45째 offset in each quadrant, and this non-linear property leads to fractional spurs. The proposed 45째 phase rotator with digital compensation reduces the fractional spur by 18.57 dB at most, and average improvement of fractional tones is 7.89 dB in 2 MHz frequency step measurement.
- KSP 제안 키워드
- All-digital phase-locked loop(ADPLL), Current-mode(CM), Digital compensation, Fractional spur, Non-linear property, Reduction technique, digital phase locked loop(DPLL), fractional-n, phase error, phase interpolator, phase rotator