상세정보
학술지
Low-Noise Wideband PLL with Dual-Mode Ring-VCO
- 발행일
- 201009
- 출처
- Electronics Letters, v.46 no.20, pp.1368-1370
- ISSN
- 0013-5194
- 출판사
- IET
- 협약과제
- 10MB1700, 45nm급 혼성 SoC용 아날로그 회로기술, 권종기
- 초록
- A low-jitter 110MHz-to-620MHz phase-locked loop (PLL) that includes a low-noise wide-frequency-range ring oscillator with a dual-mode operation is presented. The measurement results using a 65nm low-power CMOS process show that the proposed PLL achieves as low as a 2.5ps RMS jitter at 600MHz of output frequency while consuming 2.7mW at a 1.2V supply. The die area is only 0.09mm2. © 2010 The Institution of Engineering and Technology.
- KSP 제안 키워드
- CMOS Process, Dual-mode ring, Low noise, Output frequency, Phase locked loop(PLL), Wide frequency, dual-mode operation, low jitter, low-power CMOS, measurement results, ring oscillator