We propose a novel process technology for fabricating a very high density n-channel trench-gate metal oxide silicon field effect transistor (MOSFET) by using an oxide spacer and self-aligned techniques. Due to this nano-scale technology, the cell pitch of the trench-gate MOSFET could be reduced to 3.0 μm, which resulted in an increase in the cell density and in current driving capability. By reducing masks to four layers, a cost-effective process was available. The self-aligned technique also permits a narrow width of the trench gate on the scale of 300 nm. The fabricated device exhibits a specific on-resistance of 1.4 m廓쨌cm2 for a breakdown voltage of 114.8 V. Moreover, the long-term gate oxide's integrity was improved by adopting corner rounding and hydrogen annealing technologies.
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J. Kim et. al, "Trends in Lightweight Kernel for Many core Based High-Performance Computing", Electronics and Telecommunications Trends. Vol. 32, No. 4, 2017, KOGL Type 4: Source Indication + Commercial Use Prohibition + Change Prohibition
J. Sim et.al, “the Fourth Industrial Revolution and ICT – IDX Strategy for leading the Fourth Industrial Revolution”, ETRI Insight, 2017, KOGL Type 4: Source Indication + Commercial Use Prohibition + Change Prohibition
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