상세정보
학술지
Dual-Mode VCO Gain Topology for Reducing In-Band Noise and Reference Spur of PLL in 65 nm CMOS
- 발행일
- 201003
- 출처
- Electronics Letters, v.46 no.5, pp.335-337
- ISSN
- 0013-5194
- 출판사
- IET
- 협약과제
- 09MB2100, 45nm급 혼성 SoC용 아날로그 회로기술, 권종기
- 초록
- A new topology in PLL architecture dual-mode KVCO (DMK) to reduce in-band noise and reference spurs is presented. The DMK PLL also adopts the technique to shrink the spurs by modulating the control voltage. The prototype DMK PLL is implemented in a 65nm CMOS and shows about 3ps RMS jitter, phase noise of -107 and -109dBc/Hz at 100kHz, 1MHz offset frequency and reference spur of 68.5dBc. © 2010 The Institution of Engineering and Technology.
- KSP 제안 키워드
- 65nm CMOS, VCO gain, control voltage, dual-mode VCO, in-band noise, phase noise, reference spurs