BROWSE
Detail
Journal Article
Dual-mode VCO gain topology for reducing in-band noise and reference spur of PLL in 65 nm CMOS
Cited 9 time in 
Share 
Share
- Authors
- S.-H. Cho, H.-D. Lee, K.-D. Kim, S.-T. Ryu, J.-K. Kwon
- Issue Date
- 2010-03
- Citation
- Electronics Letters, v.46, no.5, pp.335-337
- ISSN
- 0013-5194
- Publisher
- IET
- Language
- English
- Type
- Journal Article
- Abstract
- A new topology in PLL architecture dual-mode KVCO (DMK) to reduce in-band noise and reference spurs is presented. The DMK PLL also adopts the technique to shrink the spurs by modulating the control voltage. The prototype DMK PLL is implemented in a 65nm CMOS and shows about 3ps RMS jitter, phase noise of -107 and -109dBc/Hz at 100kHz, 1MHz offset frequency and reference spur of 68.5dBc. © 2010 The Institution of Engineering and Technology.
- KSP Keywords
- 65nm CMOS, VCO gain, control voltage, dual-mode VCO, in-band noise, phase noise, reference spur