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Conference Paper
Analysis of High-Density Trench Gate MOSFET using SIde-wall Spacer Technology
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- Issue Date
- 2016-01
- Citation
- International Conference on Electronics, Information and Communication (ICEIC) 2016, pp.751-752
- Language
- English
- Type
- Conference Paper
- Abstract
- This paper describes electrical characteristics such as on-resistance, output driving current, breakdown voltage and gate oxide. In order to improve the integration density of trench gate MOSFET, we adopt novel oxide spacer and self-aligned techniques using 4 mask layers. The fabricated device with 300 nano-meter trench width and 3.3 ln cell pitch showed a low specific on-resistance of 0.4 mO.cm2 under a breakdown voltage of ll4V. The variation of current driving capability depending on cell density was also investigated.