상세정보
학술대회
100 Gb/s Photoreceiver Module based on 4ch × 25 Gb/s Verticalillumination-type Ge-on-Si Photodetectors and Amplifier Circuits
- 발행일
- 201603
- 출처
- Silicon Photonics XI (SPIE 9752), v.9752, pp.1-7
- 초록
- We present the performance of 4-channel × 25 Gb/s all-silicon photonic receivers based on hybrid-integrated vertical Ge-on-bulk-silicon photodetectors with 65nm bulk CMOS front-end circuits, characterized over 100 Gb/s. The sensitivity of a single-channel Ge photoreceiver module at a BER = 10-12 was measured -11 dBm at 25 Gb/s, whereas, the measured sensitivity of a 4-ch Ge photoreceiver was -10.06 ~ -10.9 dBm for 25Gb/s operation of each channel, and further improvement is in progress. For comparison, we will also present the performance of a 4-ch × 25 Gb/s photoreceiver module, where commercial InP HBT-based front-end circuits is used, characterized up to 100 Gb/s.
- KSP 제안 키워드
- 100 Gb/s, Bulk CMOS, CMOS Front-End, Ge-on-Si, InP HBT, Silicon photonics, Single Channel, bulk silicon