상세정보
학술지
Evaluation of Seebeck Coefficients in n- and p-type Silicon Nanowires Fabricated by Complementary Metal-Oxide-Semiconductor Technology
- 발행일
- 201209
- 출처
- Nanotechnology, v.23 no.40, pp.1-7
- ISSN
- 0957-4484
- 출판사
- Institute of Physics (IOP)
- 협약과제
- 11ZE1100, ETRI 연구역량 강화를 위한 R&D체계 구축 및 Seed형 기술개발을 위한 창의형 연구 사업, 지경용
- 초록
- Silicon-based thermoelectric nanowires were fabricated by using complementary metal-oxide-semiconductor (CMOS) technology. 50nm width n- and p-type silicon nanowires (SiNWs) were manufactured using a conventional photolithography method on 8inch silicon wafer. For the evaluation of the Seebeck coefficients of the silicon nanowires, heater and temperature sensor embedded test patterns were fabricated. Moreover, for the elimination of electrical and thermal contact resistance issues, the SiNWs, heater and temperature sensors were fabricated monolithically using a CMOS process. For validation of the temperature measurement by an electrical method, scanning thermal microscopy analysis was carried out. The highest Seebeck coefficients were 169.97μV K 1 and 152.82μV K 1 and the highest power factors were 2.77mWm 1K 2 and 0.65mWm 1K 2 for n- and p-type SiNWs, respectively, in the temperature range from 200 to 300K. The larger power factor value for n-type SiNW was due to the higher electrical conductivity. The total Seebeck coefficient and total power factor for the n-and p-leg unit device were 157.66μV K 1 and 9.30mWm 1K 2 at 300K, respectively. © 2012 IOP Publishing Ltd.
- KSP 제안 키워드
- CMOS Process, Complementary metal-oxide-semiconductor(CMOS), Contact resistance(73.40.Cg), Electrical conductivity(EC), Metal-oxide(MOX), Microscopy analysis, N-type, Power factor(P.F), Seebeck coefficient, Semiconductor technology, Silicon wafer