상세정보
학술대회
Performance of On-Chip Multiprocessors for Vision Tasks
- 발행일
- 200005
- 출처
- International Parallel and Distributed Processing Symposium (IPDPS) 2000 (LNCS 1800), pp.242-249
- 협약과제
- 99MC2500, 고성능 멀티미디어 서버 기술개발, 윤석한
- 초록
- Computer vision is a challenging data intensive application. Currently, superscalar architectures dominate the processor marketplace. As more transistors become available on a single chip, the "on-chip multiprocessor" has been proposed as a promising alternative to processors based on the superscalar architecture. This paper examines the performance of vision benchmark tasks on an on-chip multiprocessor. To evaluate the performance, a program-driven simulator and its programming environment were developed. DARPA IU benchmarks were used for evaluation purposes. The benchmark includes integer, floating point, and extensive data movement operations. The simulation results show that the proposed on-chip multiprocessor can exploit thread-level parallelism effectively. © 2000 Springer-Verlag Berlin Heidelberg.
- KSP 제안 키워드
- Computer Vision(CV), Data intensive applications, Data movement, Floating point, On-chip, Programming environment, Single-Chip, Superscalar architecture, chip multiprocessor, simulation results, thread-level parallelism