BROWSE
Detail
Conference Paper
Performance of On-Chip Multiprocessors for Vision Tasks (Summary)
Cited 2 time in 
Share 
Share
- Issue Date
- 2000-05
- Citation
- International Parallel and Distributed Processing Symposium (IPDPS) 2000 (LNCS 1800), pp.242-249
- Publisher
- Springer
- Language
- English
- Type
- Conference Paper
- Abstract
- Computer vision is a challenging data intensive application. Currently, superscalar architectures dominate the processor marketplace. As more transistors become available on a single chip, the "on-chip multiprocessor" has been proposed as a promising alternative to processors based on the superscalar architecture. This paper examines the performance of vision benchmark tasks on an on-chip multiprocessor. To evaluate the performance, a program-driven simulator and its programming environment were developed. DARPA IU benchmarks were used for evaluation purposes. The benchmark includes integer, floating point, and extensive data movement operations. The simulation results show that the proposed on-chip multiprocessor can exploit thread-level parallelism effectively. © 2000 Springer-Verlag Berlin Heidelberg.
- KSP Keywords
- Computer Vision(CV), Data intensive applications, Data movement, Floating point, On-chip, Programming environment, Single chip, Superscalar architecture, chip multiprocessor, simulation results, thread-level parallelism