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Journal Article
Silicon Photonic Receiver and Transmitter Operating Up to 36 Gb/s for λ~1550 nm
- Authors
- Jiho Joo, Ki-Seok Jang, Sang Hoon Kim, In Gyoo Kim, Jin Hyuk Oh, Sun Ae Kim, Gyu-Seob Jeong, Yoonsoo Kim, Jun-Eun Park, Sungwoo Kim, Hankyu Chi, Deog-Kyoon Jeong, Gyungock Kim
- Issue Date
- 2015-05
- Citation
- Optics Express, v.23, no.9, pp.12232-12243
- ISSN
- 1094-4087
- Publisher
- Optical Society of America(OSA)
- Language
- English
- Type
- Journal Article
- Abstract
- We present the hybrid-integrated silicon photonic receiver and transmitter based on silicon photonic devices and 65 nm bulk CMOS interface circuits operating over 30 Gb/s with a 10-12 bit error rate (BER) for 款 ~1550nm. The silicon photonic receiver, operating up to 36 Gb/s, is based on a vertical-illumination type Ge-on-Si photodetector (Ge PD) hybrid-integrated with a CMOS receiver front-end circuit (CMOS Rx IC), and exhibits high sensitivities of -11 dBm, -8 dBm, and -2 dBm for data rates of 25 Gb/s, 30 Gb/s and 36 Gb/s, respectively, at a BER of 10-12. The measured energy efficiency of the Si-photonic receiver is 2.6 pJ/bit at 25 Gb/s with an optical input power of -11 dBm, and 2.1 pJ/bit at 36 Gb/s with an optical power of -2 dBm. The hybrid-integrated silicon photonic transmitter, comprised of a depletion-type Mach-Zehnder modulator (MZM) and a CMOS driver circuit (CMOS Tx IC), shows better than 5.7 dB extinction ratio (ER) for 25 Gb/s, and 3 dB ER for 36 Gb/s. The silicon photonic transmitter achieves the data transmission with less than 10-15 BER at 25 Gb/s, 10-14 BER at 28 Gb/s, and 6 × 10-13 BER with the energy efficiency of ~6 pJ/bit at 30 Gb/s.
- KSP Keywords
- 1550 nm, 65 nm, Bit Error Rate(And BER), Bulk CMOS, CMOS Receiver, CMOS driver, Data transmission, Driver circuit, Energy Efficiency, Front-End Circuit, Ge-on-Si
This work is distributed under the term of Creative Commons License (CCL)
(CC BY)
(CC BY)
