BROWSE
Detail
Journal Article
High Performance and FPGA Implementation of Scalable Video Encoder
Cited - time in 
Share 
Share
- Authors
- Seongmo Park, Hyunmi Kim, Kyungjin Byun
- Issue Date
- 2014-12
- Citation
- IEIE Transactions on Smart Processing and Computing, v.3, no.6, pp.353-357
- ISSN
- 2287-5255
- Publisher
- 대한전자공학회 (IEEK)
- Language
- English
- Type
- Journal Article
- Abstract
- A new video compression standard called High Efficiency Video Coding (HEVC) has recently been released onto the market. HEVC provides higher coding performance compared to previous standards, but at the cost of a significant increase in encoding complexity, particularly in motion estimation (ME). At the same time, the computing capabilities of Graphics Processing Units (GPUs) have become more powerful. This paper proposes a parallel integer-pel ME (IME) algorithm for HEVC on GPU using the Compute Unified Device Architecture (CUDA). In the proposed IME, concurrent parallel reduction (CPR) is introduced. CPR performs several parallel reduction (PR) operations concurrently to solve two problems in conventional PR; low thread utilization and high thread synchronization latency. The proposed encoder reduces the portion of IME in the encoder to almost zero with a 2.3% increase in bitrate. In terms of IME, the proposed IME is up to 172.6 times faster than the IME in the HEVC reference model.
- KSP Keywords
- Coding performance, Compute Unified Device Architecture(CUDA), FPGA Implementation, High Efficiency Video coding(HEVC), High performance, Motion estimation(ME), Parallel reduction, Reference model, Scalable Video, Video Compression, encoding complexity