BROWSE
Detail
Journal Article
A 1.8∼3.2-GHz fully differential GaAs MESFET PLL
Cited 3 time in 
Share 
Share
- Authors
- Tae-Sik Cheung, Bhum-Cheol Lee, Eun-Chang Choi, Woo-Young Choi
- Issue Date
- 2001-04
- Citation
- IEEE Journal of Solid-State Circuits, v.36, no.4, pp.605-610
- ISSN
- 0018-9200
- Publisher
- IEEE
- Language
- English
- Type
- Journal Article
- Abstract
- A 1.8-3.2-GHz fully differential phase-locked loop (PLL) is realized for asynchronous transfer mode clock generation applications. The PLL includes a new differential voltage controlled oscillator with the wide tuning range of 1.74 ~ 3.40 GHz and a new differential charge pump with improved hold characteristics. The PLL is implemented with 0.5-μm GaAs MESFET technology. The experimental results show that the proposed PLL has a lock range of 1.8 ~ 3.2 GHz and its output RMS jitter is at most 5.0 ps (0.015 UI) at 3.2 GHz.
- KSP Keywords
- Asynchronous transfer mode, Charge pump, Clock generation, Differential charge, Differential voltage, GaAs MESFET, Wide Tuning Range, fully differential, phase-locked loop(PLL), voltage-controlled oscillator(VCO)