상세정보
학술지
A 1.8/spl sim/3.2-GHz fully differential GaAs MESFET PLL
- 발행일
- 200104
- 출처
- IEEE Journal of Solid-State Circuits, v.36 no.4, pp.605-610
- ISSN
- 0018-9200
- 출판사
- IEEE
- 협약과제
- 00HT1100, ATM교환시스템개발, 박권철
- 초록
- A 1.8-3.2-GHz fully differential phase-locked loop (PLL) is realized for asynchronous transfer mode clock generation applications. The PLL includes a new differential voltage controlled oscillator with the wide tuning range of 1.74 ~ 3.40 GHz and a new differential charge pump with improved hold characteristics. The PLL is implemented with 0.5-μm GaAs MESFET technology. The experimental results show that the proposed PLL has a lock range of 1.8 ~ 3.2 GHz and its output RMS jitter is at most 5.0 ps (0.015 UI) at 3.2 GHz.
- KSP 제안 키워드
- Asynchronous transfer mode, Charge pump, Clock generation, Differential charge, Differential voltage, Fully differential, GaAs MESFET, Voltage controlled oscillator(VCO), Wide Tuning Range, phase-locked loop(PLL)