BROWSE
Detail
Conference Paper
Design and Simulation of 622 Mb/s Burst Mode Clock Recovery Circuit Using Digital Logic Devices
Cited - time in 
Share 
Share
- Authors
- Jae-Seung Hwang, Chul-Soo Park, Hyuek-Jae Lee, Jee-Yon Choi, Keun-Young Kim, ChangSoo Park
- Issue Date
- 2001-07
- Citation
- 한국통신학회 종합 학술 발표회 (하계) 2001, pp.1743-1746
- Publisher
- 한국통신학회
- Language
- English
- Type
- Conference Paper
- KSP Keywords
- Burst-mode, Clock recovery(CR), Design and simulation, Digital logic, logic devices