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Conference Paper
A 2.5 Gbit/s pipelined routing engine for input-queued ATM switches
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- Authors
- Gab Joong Jeong, Jung-Hee Lee, Bhum Cheol Lee
- Issue Date
- 2001-08
- Citation
- IEEE Region 10 Conference (TENCON) 2001, pp.377-380
- Publisher
- IEEE
- Language
- English
- Type
- Conference Paper
- Abstract
- This paper presents the design of a 2.5 Gbit/s pipelined virtual output queue routing engine for an input-queued ATM switch, which has a serial crossbar structure. The proposed routing engine has been designed for wire-speed routing with a pipelined buffer management. It provides the tolerance of requests and grants data transmission latency between the routing engine and central arbiter using a new request control method that is based on a high-speed shifter. The designed routing engine has been implemented in a field programmable gate array chip with a 77 MHz operating frequency, a 900-pin fine ball grid array package, and 16/spl times/16 switch size.
- KSP Keywords
- Buffer management, Crossbar Structure, Data transmission latency, Field-Programmable Gate Array(FPGA), High Speed, Operating frequency, array chip, ball grid array, control method, wire speed