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Digital Compensator for Large Phase-Error Glitches in Digital PLL
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- Authors
- Ja-Yol Lee, Mi-Jeong Park, Cheon Soo Kim, Hyun-Kyu Yu
- Issue Date
- 2012-12
- Citation
- Electronics Letters, v.48, no.19, pp.1184-1185
- ISSN
- 0013-5194
- Publisher
- IET
- Language
- English
- Type
- Journal Article
- Abstract
- Proposed is a digital compensator that is employed in a digital phaselocked loop (PLL) to avoid big phase-error downfalls caused by the large output glitches originating from a high-speed counter based on standard logic cells. The proposed compensation mechanism enables the PLL to acquire a desired frequency under irregular voltage and temperature.
- KSP Keywords
- Compensation mechanism, Digital PLL, High-Speed Counter, phase-locked loop(PLL), process-voltage-temperature(PVT), standard logic cells