상세정보
학술지
Digital Compensator for Large Phase-Error Glitches in Digital PLL
- 발행일
- 201212
- 출처
- Electronics Letters, v.48 no.19, pp.1184-1185
- ISSN
- 0013-5194
- 출판사
- IET
- 협약과제
- 11MB5600, 2세대/3세대/4세대 이동통신을 지원하는 RFIC/PAM 개발, 유현규
- 초록
- Proposed is a digital compensator that is employed in a digital phaselocked loop (PLL) to avoid big phase-error downfalls caused by the large output glitches originating from a high-speed counter based on standard logic cells. The proposed compensation mechanism enables the PLL to acquire a desired frequency under irregular voltage and temperature.
- KSP 제안 키워드
- Compensation mechanism, Digital PLL, High-Speed Counter, Phase locked loop(PLL), process-voltage-temperature(PVT), standard logic cells