상세정보
학술지
A 7.1-GB/s low-power rendering engine in 2-D array-embedded memory logic CMOS for portable multimedia system
- 저자
- 박용하, 한선호, Jung-Hwan Lee, Hoi-Jun Yoo
- 발행일
- 200106
- 출처
- IEEE Journal of Solid-State Circuits, v.36 no.6, pp.944-955
- ISSN
- 0018-9200
- 출판사
- IEEE
- 초록
- A single-chip rendering engine that consists of a DRAM frame buffer, a SRAM serial access memory, pixel/edge processor array and 32-b RISC core is proposed for low-power three-dimensional (3-D) graphics in portable systems. The main features are two-dimensional (2-D) hierarchical octet tree (HOT) array structure with bandwidth amplification, three dedicated network schemes, virtual page mapping, memory-coupled logic pipeline, low-power operation, 7.1-GB/s memory bandwidth, and 11.1-Mpolygon/s drawing speed. The 56-mm2 prototype die integrating one edge processor, eight pixel processors, eight frame buffers, and a RISC core are fabricated using 0.35-μm CMOS embedded memory logic (EML) technology with four poly layers and three metal layers. The fabricated test chip, 590 mW at 100-MHz 3.3-V operation, is demonstrated with a host PC through a PCI bridge.
- KSP 제안 키워드
- 2-D array, Dedicated network, Drawing speed, Embedded memory, Frame buffer, Memory bandwidth, Multimedia systems, Portable System, Processor array, RISC core, Rendering engine