상세정보
학술대회
An efficient architecture of DCTQ module in MPEG-4 video codec
- 발행일
- 200205
- 출처
- International Symposium on Circuits and Systems (ISCAS) 2002, pp.777-780
- 협약과제
- 02MB2100, 멀티미디어 이동통신 단말기용 고집적 시스템 IC 개발, 김종대
- 초록
- In this paper, a VLSI architecture for DCTQ module, which consists of 2D-DCT, quantization, AC/DC prediction block, scan conversion, inverse quantization and 2D-IDCT, is presented. The architecture of the DCTQ is designed to handle a macroblock data within 1064 cycles and suitable for MPEG-4 video codec handling CIF image formats. Only single 1-D DCT/IDCT cores are used for the design instead of 2-D DCT/IDCT, respectively. 1-bit serial distributed arithmetic architecture is adopted for 1-D DCT/IDCT to reduce the hardware area in this architecture. As the result, the maximum utilization of hardware can be achieved, and power consumption can be minimized. The proposed design is operated on 27MHz clock. The area is 50% smaller than the previous methods with 2D-DCT and IDCT. The experimental results show that the accuracy of DCT and IDCT meet the IEEE specification.
- KSP 제안 키워드
- 2D-DCT, 2D-IDCT, Bit Serial, Distributed Arithmetic Architecture, Image Format, MPEG-4 video, Power Consumption, Scan Conversion, VLSI Architecture, Video Codec, efficient architecture