BROWSE
Detail
Conference Paper
An efficient architecture of DCTQ module in MPEG-4 video codec
Cited 2 time in 
Download 1 time
Share 
Download 1 time
Share
- Authors
- Kibum suh, Seongmo Park, Seongmin Kim, Bontae Koo, Igkyun Kim, Kyungsoo Kim, Hanjin Cho
- Issue Date
- 2002-05
- Citation
- International Symposium on Circuits and Systems (ISCAS) 2002, pp.777-780
- Language
- English
- Type
- Conference Paper
- Project Code
- 02MB2100, Development of Platform based system integrated circuit design technology for multimedia mobile communication terminals, Kim Jongdae
- Abstract
- In this paper, a VLSI architecture for DCTQ module, which consists of 2D-DCT, quantization, AC/DC prediction block, scan conversion, inverse quantization and 2D-IDCT, is presented. The architecture of the DCTQ is designed to handle a macroblock data within 1064 cycles and suitable for MPEG-4 video codec handling CIF image formats. Only single 1-D DCT/IDCT cores are used for the design instead of 2-D DCT/IDCT, respectively. 1-bit serial distributed arithmetic architecture is adopted for 1-D DCT/IDCT to reduce the hardware area in this architecture. As the result, the maximum utilization of hardware can be achieved, and power consumption can be minimized. The proposed design is operated on 27MHz clock. The area is 50% smaller than the previous methods with 2D-DCT and IDCT. The experimental results show that the accuracy of DCT and IDCT meet the IEEE specification.
- KSP Keywords
- 2D-DCT, 2D-IDCT, Bit Serial, Distributed Arithmetic Architecture, Image Format, MPEG-4 video, Power Consumption, Scan Conversion, VLSI Architecture, Video Codec, efficient architecture