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학술대회 Design of new DSP instructions and their hardware architecture for the Viterbi decoding algorithm
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저자
Jung Hoo Lee, 이재성, Myung H. Sunwoo, Kyung Ho Kim
발행일
200205
출처
International Symposium on Circuits and Systems (ISCAS) 2002, pp.561-564
DOI
https://dx.doi.org/10.1109/ISCAS.2002.1010765
협약과제
01MC2600, 인터넷 서버용 차세대 클러스터 연결망 기술개발, 김용연
초록
This paper proposes new DSP instructions and their architecture which efficiently and rapidly implements the Viterbi decoding algorithm. The proposed architecture, supporting typical signal processing functions as in existing DSP chips, consists of an array of operational units and data path structures adequate to the Viterbi algorithm. While existing DSP chips perform Viterbi decoding at the rate of about several dozen kbps, the proposed architecture can give the rate of 6.25 Mbps on 100 MHz DSP chips, which is nearly the same performance as that of custom-designed Viterbi processors. Therefore, the architecture can meet the standard of IMT-2000 having the 2Mbps data rate. The proposed architecture will be implemented in the form of an ASDSP (Application-Specific Digital Signal Processor) chip.
KSP 제안 키워드
100 MHz, Application-specific, Digital signal processor(DSP), Hardware Architecture, IMT-2000, Signal Processing, Viterbi Algorithm, Viterbi decoding, data path, data rate, decoding algorithm