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Conference Paper
The effect of via size on fine pitch and high density solder bumps for wafer level packaging
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- Issue Date
- 2002-05
- Citation
- Electronic Components and Technology Conference (ECTC) 2002, pp.1178-1181
- Publisher
- IEEE
- Language
- English
- Type
- Conference Paper
- Abstract
- This study investigated how the shapes of high density electroplated bump and reflowed bumps depend on via size. The solder bump was fabricated by subsequent processes as follows. After sputtering a Ti/Cu seed layer on a 5-inch Si-wafer, a thick photoresist for via formation was obtained by multi-coating, and vias with various diameters were defined by a conventional photolithography technique using a contact alinger with an I-line source. After via formation, eutectic solder bumps were electroplated. After reflow, the reflowed bump diameters at the bottom were unchanged compared with the electroplated diameters. The electroplated bump and reflowed bump shapes, however, depended significantly on the via size. The heights of the electroplated bumps and reflowed bumps increased with a larger via, while the aspect ratio of bumps decreased. To obtain high density bumps, the bump pitch was decreased so that the nearest bumps touched. The touching between the nearest bumps occurred during the over-plating procedure but not during the reflowing procedure because the mushroom diameter formed by over-plating was larger than the reflowed bump diameter. This study demonstrated that an arrangement in zig-zag rows is effective in realizing flip chip interconnect bumps with both a high density and high aspect ratio.
- KSP Keywords
- Bump pitch, Cu seed layer, Fine pitch, High aspect ratio, High-density, Line source, Multi-coating, Photolithography technique, Solder bump, Thick photoresist, Wafer Level Packaging