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A high speed direct digital frequency synthesizer using a low power pipelined parallel accumulator
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- Authors
- Byung-Do Yang, Lee-Sup Kim, Hyun-Kyu Yu
- Issue Date
- 2002-05
- Citation
- International Symposium on Circuits and Systems (ISCAS) 2002, pp.373-376
- Publisher
- IEEE
- Language
- English
- Type
- Conference Paper
- Abstract
- A new high speed direct digital frequency synthesizer (DDFS) using a low power pipelined parallel accumulator (PPA) is proposed. The PPA uses both pipelining and paralleling techniques to increase speed and to reduce power consumption. The PPA attains benefits of the pipelined accumulator and the parallel accumulator. The 2-pipelined 2-parallel PPA only consumes 66% and 69% power of the 4-pipelined accumulator and the 4-parallel accumulator respectively with the same throughput. The PPA can achieve higher throughput with smaller area and less power consumption in lower clock frequency. All circuit simulations and implementations are based on a 0.35um CMOS technology with VCC = 3.3V.
- KSP Keywords
- 2-parallel, CMOS Technology, Clock frequency, Direct digital frequency synthesizer(DDFS), High Speed, Low-Power, Power Consumption, circuit simulation