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Conference Paper
A 0.58-1 Gb/s CMOS data recovery circuit using a synchronous digital phase aligner
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- Authors
- T.S. Cheung, B.C. Lee
- Issue Date
- 2002-08
- Citation
- Midwest Symposium on Circuits and Systems (MWSCAS) 2002, pp.385-388
- Language
- English
- Type
- Conference Paper
- Abstract
- A data recovery circuit using a newly proposed synchronous digital phase aligner is realized for multi-link applications. The proposed circuit is implemented with 0.35 /spl mu/m CMOS process technology. The experimental results show that the proposed circuit successfully recovers incoming 0.58-1 Gb/s of 2/sup 31/-1 pseudo random bit sequence with less than 10/sup -14/ of bit error rate.
- KSP Keywords
- Bit Error Rate(And BER), CMOS process technology, Data recovery circuit, Multi-link, Pseudo-random, Random bit