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Detail
Journal Article
A DSP Architecture for High‐Speed FFT in OFDM Systems
- Authors
- Jae Sung Lee, Jeong Hoo Lee, Myung H. Sunwoo, Sang Man Moh, Seong Keun Oh
- Issue Date
- 2002-10
- Citation
- ETRI Journal, v.24, no.5, pp.391-397
- ISSN
- 1225-6463
- Publisher
- 한국전자통신연구원 (ETRI)
- Language
- English
- Type
- Journal Article
- Abstract
- This paper presents digital signal processor (DSP) instructions and their data processing unit (DPU) architecture for high-speed fast Fourier transforms (FFTs) in orthogonal frequency division multiplexing (OFDM) systems. The proposed instructions jointly perform new operation flows that are more efficient than the operation flow of the multiply and accumulate (MAC) instruction on which existing DSP chips heavily depend. We further propose a DPU architecture that fully supports the instructions and show that the architecture is two times faster than existing DSP chips for FFTs. We simulated the proposed model with a Verilog HDL, performed a logic synthesis using the 0.35 μm standard cell library and then verified the functions thoroughly.
- KSP Keywords
- Data processing, Digital signal processor(DSP), Fast Fourier transform, High Speed, Logic synthesis, Multiply and Accumulate(MAC), OFDM systems, Operation flow, Orthogonal frequency division Multiplexing(OFDM), Processing unit, Proposed model